PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 202
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PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 202 of 548
- Download datasheet (5Mb)
PIC18F87K22 FAMILY
FIGURE 14-4:
14.8.2
The Timer1 gate source can be selected from one of
four sources. Source selection is controlled by the
T1GSSx (T1GCON<1:0>) bits (see Table 14-4).
TABLE 14-4:
The polarity for each available source is also selectable,
controlled by the T1GPOL bit (T1GCON<6>).
14.8.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
14.8.2.2
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
DS39960B-page 202
T1GSS<1:0>
00
01
10
11
TMR1GE
T1GPOL
T1GVAL
T1G_IN
Timer1
T1CKI
TIMER1 GATE SOURCE
SELECTION
T1G Pin Gate Operation
Timer2 Match Gate Operation
Timer1 Gate Pin
TMR2 to Match PR2
(TMR2 increments to match PR2)
Comparator 1 Output
(comparator logic high output)
Comparator 2 Output
(comparator logic high output)
TIMER1 GATE SOURCES
TIMER1 GATE COUNT ENABLE MODE
Timer1 Gate Source
N
Preliminary
N + 1
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1 gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on T1GPOL, Timer1 increments differently
when TMR2 matches PR2. When T1GPOL = 1, Timer1
increments for a single instruction cycle following a
TMR2 match with PR2. When T1GPOL = 0, Timer1
increments continuously except for the cycle following
the match when the gate signal goes from low-to-high.
14.8.2.3
The output of Comparator 1 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer1 will
increment depending on the transitions of the
CMP1OUT (CMSTAT<5>) bit.
14.8.2.4
The output of Comparator 2 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer1 will
increment depending on the transitions of the
CMP2OUT (CMSTAT<6>) bit.
N + 2
Comparator 1 Output Gate
Operation
Comparator 2 Output Gate
Operation
2010 Microchip Technology Inc.
N + 3
N + 4
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