PIC18F4431-I/ML Microchip Technology, PIC18F4431-I/ML Datasheet - Page 169

• Manufacturer Part Number: PIC18F4431-I/ML
• Description: IC PIC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

16.1.5
The following is a summary of functional operation
upon entering any of the Input Capture modes:
1.
2.
FIGURE 16-7:
© 2007 Microchip Technology Inc.
TMR5 Reset
Note 1: Timer5 is only reset and enabled (assuming TMR5ON = 0 and T5MOD = 1) when the Special Event Trigger Reset is
TMR5ON
After the module is configured for one of the
Capture modes by setting the Capture Mode
Select
detected edge captures the Timer5 value and
stores it in the CAPxBUF register. The timer is
then reset (depending on the setting of
CAPxREN bit) and starts to increment according
to its settings (see Figure 16-4, Figure 16-5 and
Figure 16-6).
On all edges, the capture logic performs the
following:
a)
b)
c)
d)
e)
f)
CAP1 Pin
TMR5
IC1IF
OSC
Input Capture mode is decoded and the
active edge is identified.
The CAPxREN bit is checked to determine
whether Timer5 is reset or not.
On every active edge, the Timer5 value is
recorded in the Input Capture Buffer
(CAPxBUF).
Reset Timer5 after capturing the value of
the timer when the CAPxREN bit is
enabled. Timer5 is reset on every active
capture edge in this case.
On all continuing capture edge events,
repeat steps (a) through (d) until the opera-
tional mode is terminated, either by user
firmware, POR or BOR.
The timer value is not affected when switch-
ing into and out of various Input Capture
modes.
(1)
ENTERING INPUT CAPTURE MODE
AND CAPTURE TIMING
enabled for the Timer5 Reset input. TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the
event capture. With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger
Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must
be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111).
bits
Q1
(CAPxM3:CAPxM0),
Q2
XXXX
CAPx INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER
Q3
Q4
Q1
Q2
the
PIC18F2331/2431/4331/4431
Q3
first
Q4
Preliminary
Q1
Q2
16.1.6
Every input capture trigger can optionally reset
(TMR5). The Capture Reset Enable bit, CAPxREN,
gates the automatic Reset of the time base of the cap-
ture event with this enable Reset signal. All capture
events reset the selected timer when CAPxREN is set.
Resets are disabled when CAPxREN is cleared (see
Figure 16-4, Figure 16-5 and Figure 16-6).
16.1.7
There are four operating modes for which the IC
module can generate an interrupt and set one of the
Interrupt Capture Flag bits (IC1IF, IC2QEIF or
IC3DRIF). The interrupt flag that is set depends on the
channel in which the event occurs. The modes are:
• Edge Capture
• Period Measurement Event
• Pulse-Width Measurement Event
• State Change Event (CAPxM3:CAPxM0 = 1000)
The timing of interrupt and Special Event Trigger
events is shown in Figure 16-7. Any active edge is
detected on the rising edge of Q2 and propagated on
the rising edge of Q4 rising edge. If an active edge
happens to occur any later than this (on the falling edge
of Q2, for example), then it will be recognized on the
next Q2 rising edge.
Q3
Note:
(CAPxM3:CAPxM0 = 0001, 0010, 0011 or 0100)
(CAPxM3:CAPxM0 = 0101)
(CAPxM3:CAPxM0 = 0110 or 0111)
Note:
Q4
TIMER5 RESET
The CAPxREN bit has no effect in
Pulse-Width Measurement mode.
IC INTERRUPTS
The Special Event Trigger is generated only
in the Special Event Trigger mode on the
CAP1 input (CAP1M2:CAP1M0 = 1110
and 1111). IC1IF interrupt is not set in this
mode.
Q1
Q2
0000
Q3
Q4
Q1
DS39616C-page 167
Q2
0001
Q3
Q4