PIC18F4431-I/ML Microchip Technology, PIC18F4431-I/ML Datasheet - Page 394

• Manufacturer Part Number: PIC18F4431-I/ML
• Description: IC PIC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
Timer5 ............................................................................... 147
Timing Diagrams
DS39616C-page 392
Associated Registers ................................................ 151
Interrupt..................................................................... 150
Noise Filter ................................................................ 150
Operation .................................................................. 148
Prescaler ................................................................... 149
Special Event Trigger Output .................................... 150
Special Event Trigger Reset Input ............................ 150
16-Bit Read/Write and Write Modes ......................... 149
16-Bit Read-Modify-Write.......................................... 149
Asynchronous Reception .......................................... 236
Asynchronous Transmission ..................................... 233
Asynchronous Transmission
Automatic Baud Rate Calculation ............................. 231
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep .................... 237
Brown-out Reset (BOR) ............................................ 357
Capture/Compare/PWM (All CCP Modules) ............. 359
CAPx Interrupts and IC1
CLKO and I/O ........................................................... 356
Clock, Instruction Cycle .............................................. 63
Dead-Time Insertion for
Duty Cycle Update Times in Continuous
Duty Cycle Update Times in Continuous Up/Down
Edge Capture Mode .................................................. 164
Edge-Aligned PWM................................................... 196
EUSART Synchronous Receive
EUSART SynchronousTransmission
Example SPI Master Mode (CKE = 0) ...................... 360
Example SPI Master Mode (CKE = 1) ...................... 361
Example SPI Slave Mode (CKE = 0) ........................ 362
Example SPI Slave Mode (CKE = 1) ........................ 363
External Clock (All Modes Except PLL) .................... 354
Fail-Safe Clock Monitor............................................. 284
Input Capture on State Change ................................ 166
I
I
I
I
Low-Voltage Detect................................................... 266
Low-Voltage Detect Characteristics .......................... 349
Noise Filter ................................................................ 178
Pulse-Width Measurement Mode.............................. 165
PWM Output ............................................................. 157
PWM Output Override (Example 1) .......................... 205
PWM Output Override (Example 2) .......................... 205
PWM Override Bits in Complementary Mode ........... 203
PWM Period Buffer Updates in Continuous
PWM Period Buffer Updates in
PWM Time Base Interrupt, Continuous
2
2
2
2
C Bus Data ............................................................. 364
C Bus Start/Stop Bits.............................................. 364
C Reception (7-bit Address) ................................... 221
C Transmission (7-bit Address) .............................. 221
Continuous Count and Single-Shot................... 149
Sleep Mode....................................................... 150
(Back to Back)................................................... 233
Normal Operation.............................................. 237
Special Event Trigger........................................ 167
Complementary PWM....................................... 199
Up/Down Count Mode....................................... 196
Count Mode with Double Updates .................... 197
(Master/Slave)................................................... 368
(Master/Slave)................................................... 368
Up/Down Count Mode....................................... 194
Free-Running Mode .......................................... 194
Up/Down Count Mode....................................... 191
Preliminary
Timing Diagrams and Specifications ................................ 354
PWM Time Base Interrupt, Continuous
PWM Time Base Interrupt,
PWM Time Base Interrupt, Single-Shot Mode.......... 190
QEI Inputs When Sampled by Filter ......................... 173
QEI Reset on Period Match ...................................... 173
QEI Reset with the Index Input ................................. 174
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 238
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode).......................................... 217
SPI Mode (Slave Mode with CKE = 0)...................... 217
SPI Mode (Slave Mode with CKE = 1)...................... 218
SSP I
SSP I
Start of Center-Aligned PWM ................................... 197
Synchronous Reception
Synchronous Transmission ...................................... 239
Synchronous Transmission (Through TXEN) ........... 240
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 358
Transition for Entry to SEC_IDLE Mode ..................... 38
Transition for Entry to SEC_RUN Mode ..................... 40
Transition for Entry to Sleep Mode ............................. 36
Transition for Two-Speed Start-up
Transition for Wake From PRI_IDLE Mode ................ 37
Transition for Wake From RC_RUN Mode
Transition for Wake From SEC_RUN
Transition for Wake From Sleep (HSPLL) .................. 36
Transition to PRI_IDLE Mode ..................................... 37
Transition to RC_IDLE Mode...................................... 39
Transition to RC_RUN Mode ...................................... 41
Velocity Measurement .............................................. 176
Capture/Compare/PWM Requirements
CLKO and I/O Requirements.................................... 356
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 354
Up/Down Count Mode with Double Updates .... 192
Free-Running Mode.......................................... 189
Timer (OST), Power-up Timer (PWRT) ............ 357
V
(Master Mode, SREN) ...................................... 241
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 282
(RC_RUN to PRI_RUN) ..................................... 39
Mode (HSPLL).................................................... 38
(All CCP Modules) ............................................ 359
Requirements ................................................... 368
Requirements ................................................... 368
(Master Mode, CKE = 0)................................... 360
(Master Mode, CKE = 1)................................... 361
(Slave Mode, CKE = 0)..................................... 362
(CKE = 1).......................................................... 363
2
2
DD
C Bus Data .................................................... 366
C Bus Start/Stop Bits ..................................... 366
Rise > T
PWRT
© 2007 Microchip Technology Inc.
DD
DD
) ............................................. 57
) ........................................... 57
, V
DD
DD
DD
): Case 1 ....................... 56
): Case 2 ....................... 56
Rise T
DD
,
PWRT
) ............... 56