PIC18F4431-I/ML Microchip Technology, PIC18F4431-I/ML Datasheet - Page 69

• Manufacturer Part Number: PIC18F4431-I/ML
• Description: IC PIC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

5.9.2
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
TABLE 5-1:
© 2007 Microchip Technology Inc.
Address
FEDh POSTDEC0
FECh
FFEh
FFDh
FFCh
FFBh
FEFh
FEEh
FEBh
FEAh
FFFh
FFAh
FE9h
FE8h
FE7h
FE6h
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
POSTINC0
POSTINC1
SPECIAL FUNCTION REGISTERS
INTCON2
INTCON3
TBLPTRU
TBLPTRH
TBLPTRL
PREINC0
PREINC1
STKPTR
PLUSW1
PCLATU
PCLATH
INTCON
PLUSW0
PRODH
PRODL
TABLAT
FSR0H
FSR1H
FSR0L
WREG
FSR1L
TOSU
TOSH
Name
TOSL
INDF0
INDF1
BSR
PCL
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDEh
FDBh
FDAh
FCEh
FCBh
FCAh
FDFh
FD2h
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
POSTINC2
WDTCON
OSCCON
SSPSTAT
PREINC2
SSPCON
PLUSW2
LVDCON
ADRESH
ADCON0
ADCON1
ADCON2
STATUS
SSPBUF
SSPADD
ADRESL
TMR0H
TMR0L
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR1L
FSR2L
RCON
Name
INDF2
TMR2
PR2
—
—
PIC18F2331/2431/4331/4431
Address
FBDh
FBCh
FBEh
FBBh
FBAh
FADh
FACh
FBFh
FB2h
FB0h
FAEh
FABh
FAAh
Preliminary
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB1h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CCP1CON
CCP2CON
BAUDCTL
SPBRGH
CCPR1H
CCPR2H
EECON2
EECON1
CCPR1L
CCPR2L
QEICON
ANSEL1
ANSEL0
EEDATA
T5CON
RCREG
SPBRG
TXREG
EEADR
RCSTA
TXSTA
Name
IPR3
PIE3
IPR2
PIR2
PIR3
PIE2
—
—
—
—
—
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
OSCTUNE
ADCON3
PORTE
PORTD
PORTC
PORTB
PORTA
ADCHS
TMR5H
TMR5L
TRISE
TRISD
TRISC
TRISB
TRISA
Name
PR5H
PR5L
PIR1
LATE
LATD
LATC
LATB
PIE1
LATA
IPR1
—
—
—
—
—
—
—
Address
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
DS39616C-page 67
SEVTCMPH
FLTCONFIG
SEVTCMPL
CAP1BUFH
CAP2BUFH
PWMCON0
PWMCON1
CAP1BUFL
CAP2BUFL
CAP3BUFH
CAP3BUFL
OVDCOND
OVDCONS
CAP1CON
CAP2CON
CAP3CON
DFLTCON
PTCON0
PTCON1
PTPERH
PTPERL
PTMRH
DTCON
PTMRL
PDC0H
PDC1H
PDC2H
PDC3H
PDC0L
PDC1L
PDC2L
PDC3L
Name