PIC18F4431-I/ML Microchip Technology, PIC18F4431-I/ML Datasheet - Page 221

• Manufacturer Part Number: PIC18F4431-I/ML
• Description: IC PIC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

18.3
The SSP module, in I
functions except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCK/
SCL pin, which is the clock (SCL), and the SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<5:4> or TRISD<3:2> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 18-5:
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
• SSP Address Register (SSPADD)
© 2007 Microchip Technology Inc.
SCK/SCL
SDI/SDA
Note 1: When SSPMX = 1 in CONFIG3H:
accessible
module
SSP I
(1)
(1)
SCK/SCL is multiplexed to pin RC5, SDA/SDI
is multiplexed to pin RC4 and SDO is
multiplexed to pin RC7.
When SSPMX = 0 in CONFIG3H:
SCK/SCL is multiplexed to pin RD3, SDA/SDI
is multiplexed to pin RD2 and SDO is
multiplexed to pin RD1.
Read
2
Clock
implements
Shift
C Operation
MSb
2
C mode, fully implements all slave
SSP BLOCK DIAGRAM
(I
Stop bit Detect
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
2
Start and
C™ MODE)
the
LSb
Write
standard
Internal
Data Bus
Set, Reset
S, P bits
(SSPSTAT Reg)
2
Addr Match
C operation.
PIC18F2331/2431/4331/4431
mode
Preliminary
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
Additional information on SSP I
found in the “PIC
Manual” (DS33023).
18.3.1
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<5:4> or TRISD<3:2> set). The
SSP module will override the input state with the output
data when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 18-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit, BF, is cleared by reading the
SSPBUF register, while bit SSPOV is cleared through
software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
SSP module, are shown in timing parameter 100 and
parameter 101.
2
C specification, as well as the requirements of the
Stop bit interrupts enabled to support Firmware
Controlled Master mode
Stop bit interrupts enabled to support Firmware
Controlled Master mode
support Firmware Controlled Master mode;
Slave is Idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
C Start and Stop bit interrupts enabled to
The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
The SSP Overflow bit, SSPOV (SSPCON<6>),
was set before the transfer was received.
SLAVE MODE
®
2
Mid-Range MCU Family Reference
C mode, with the SSPEN bit set,
2
C modes to be selected:
2
C operation can be
DS39616C-page 219
2
C module.
2
C opera-