PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 138

IC MCU FLASH 12KX16 EE A/D 28DIP

PIC18F2539-I/SP

Manufacturer Part Number
PIC18F2539-I/SP
Description
IC MCU FLASH 12KX16 EE A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2539-I/SP

Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
21
Eeprom Memory Size
256Byte
Ram Memory Size
1.375KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
 Details
PIC18FXX39
REGISTER 16-4:
DS30485A-page 136
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Legend:
R = Readable bit
- n = Value at POR
SSPCON1: MSSP CONTROL REGISTER 1 (I
WCOL
R/W-0
Note:
Note:
a transmission to be started (must be cleared in software)
cleared in software)
be cleared in software)
2
2
2
2
2
2
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
C Firmware Controlled Master mode (Slave IDLE)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
SSPOV
R/W-0
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
R/W-0
CKP
/ (4 * (SSPADD+1))
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
SSPM3
R/W-0
2
C MODE)
2
SSPM2
C conditions were not valid for
R/W-0
 2002 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0

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