PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 230

• Manufacturer Part Number: PIC18F2539-I/SP
• Description: IC MCU FLASH 12KX16 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2539-I/SP

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.375KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Details

PIC18FXX39
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS30485A-page 228
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
W
Q1
=
=
=
register 'f'
Complement f
[ label ] COMF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
N, Z
The contents of register 'f' are com-
plemented. If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored back in register 'f' (default). If
‘a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
COMF
( f )
Read
0001
Q2
0x13
0x13
0xEC
→ dest
11da
REG, 0, 0
Process
Data
Q3
f [,d [,a]
ffff
destination
Write to
Q4
ffff
Preliminary
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC Address
W
REG
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
register 'f'
operation
operation
operation
Compare f with W, skip if f = W
[ label ] CPFSEQ
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
None
Compares the contents of data
memory location 'f' to the contents
of W by performing an unsigned
subtraction.
If 'f' = W
tion is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NEQUAL
EQUAL
Read
0110
Q2
No
No
No
Q2
Q2
=
=
=
=
=
≠
=
 2002 Microchip Technology Inc.
by a 2-word instruction.
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
,
then the fetched instruc-
CPFSEQ REG, 0
:
:
001a
operation
operation
operation
Process
Data
Q3
No
No
No
Q3
Q3
ffff
f [,a]
operation
operation
operation
operation
No
Q4
No
No
No
Q4
Q4
ffff