PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 93
![IC MCU FLASH 12KX16 EE A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2539-I/SP
Manufacturer Part Number
PIC18F2539-I/SP
Description
IC MCU FLASH 12KX16 EE A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18F2539-I/SP
Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
21
Eeprom Memory Size
256Byte
Ram Memory Size
1.375KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 93 of 322
- Download datasheet (7Mb)
9.4
This section is applicable only to the PIC18F4X39
devices.
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 9.6 for additional information on
the Parallel Slave Port (PSP).
EXAMPLE 9-4:
2002 Microchip Technology Inc.
Note:
CLRF
CLRF
MOVLW 0xCF
MOVWF TRISD
PORTD, TRISD and LATD
Registers
PORTD
LATD
On a Power-on Reset, these pins are
configured as digital inputs.
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
INITIALIZING PORTD
Preliminary
FIGURE 9-8:
RD LATD
Data
Bus
WR LATD
or PORTD
WR TRISD
RD TRISD
RD PORTD
Note 1:
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
PIC18FXX39
Q
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
Q
Q
EN
EN
Schmitt
Trigger
Input
Buffer
D
DS30485A-page 91
DD
and V
I/O pin
SS
.
(1)
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