PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 317

• Manufacturer Part Number: PIC18F2539-I/SP
• Description: IC MCU FLASH 12KX16 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2539-I/SP

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.375KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Details

SSPSTAT Register
Status Bits
SUBFWB .......................................................................... 246
SUBLW ............................................................................ 247
SUBWF ............................................................................ 247
SUBWFB .......................................................................... 248
SWAPF ............................................................................ 248
T
TABLAT Register ............................................................... 54
Table Pointer Operations (table) ........................................ 54
TBLPTR Register ............................................................... 54
TBLRD ............................................................................. 249
TBLWT ............................................................................. 250
Time-out Sequence ............................................................ 24
Timer0 ................................................................................ 99
Timer1 .............................................................................. 103
Timer2 .............................................................................. 107
Timer3 .............................................................................. 109
Timing Diagrams
 2002 Microchip Technology Inc.
R/W Bit ............................................................. 138, 139
Significance and the Initialization Condition
Time-out in Various Sitations ..................................... 25
16-bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit) ...................... 101
Clock Source Select (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt .................................................... 101
Prescaler. See Prescaler, Timer0
16-bit Read/Write Mode ........................................... 105
Associated Registers ............................................... 105
Operation ................................................................. 104
Oscillator .................................................................. 103
Overflow Interrupt ............................................ 103, 105
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
TMR2 to PR2 Match Interrupt .................................. 123
Associated Registers ............................................... 111
Operation ................................................................. 110
Oscillator .................................................................. 109
Overflow Interrupt ............................................ 109, 111
TMR3H Register ...................................................... 109
TMR3L Register ....................................................... 109
A/D Conversion ........................................................ 285
Acknowledge Sequence .......................................... 158
Asynchronous Reception ......................................... 175
Asynchronous Transmission .................................... 173
Asynchronous Transmission (Back to Back) ........... 173
Baud Rate Generator with Clock Arbitration ............ 152
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 272
Bus Collision During a STOP Condition
Bus Collision During a STOP Condition
Bus Collision During Repeated START
Bus Collision During Repeated START
Bus Collision During START Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge ........... 159
for RCON Register ............................................. 25
During START Condition ................................. 161
(Case 1) ........................................................... 163
(Case 2) ........................................................... 163
Condition (Case 1) ........................................... 162
Condition (Case 2) ........................................... 162
(SCL = 0) ......................................................... 161
(SDA Only) ....................................................... 160
Preliminary
Timing Diagrams Requirements
CLKO and I/O .......................................................... 271
Clock Synchronization ............................................. 145
Clock/Instruction Cycle .............................................. 36
Example SPI Master Mode (CKE = 0) ..................... 276
Example SPI Master Mode (CKE = 1) ..................... 277
Example SPI Slave Mode (CKE = 0) ....................... 278
Example SPI Slave Mode (CKE = 1) ....................... 279
External Clock (All Modes except PLL) ................... 270
First START Bit Timing ............................................ 153
I
I
I
I
I
I
I
I
I
I
Low Voltage Detect ................................................. 192
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4X39) ........................... 275
Parallel Slave Port (Read) ......................................... 97
Parallel Slave Port (Write) ......................................... 96
PWM (PWM1 and PWM2) ....................................... 274
PWM Output ............................................................ 123
Repeat START Condition ........................................ 154
RESET, Watchdog Timer (WDT), Oscillator
Slave Mode General Call Address Sequence
Slave Synchronization ............................................. 131
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 130
SPI Mode (Slave Mode with CKE = 0) ..................... 132
SPI Mode (Slave Mode with CKE = 1) ..................... 132
Stop Condition Receive or Transmit Mode .............. 158
Synchronous Reception (Master Mode, SREN) ...... 178
Synchronous Transmission ..................................... 177
Synchronous Transmission (Through TXEN) .......... 177
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 273
USART Synchronous Receive (Master/Slave) ........ 284
USART Synchronous Transmission
Wake-up from SLEEP via Interrupt .......................... 206
Master SSP I
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 280
C Bus START/STOP Bits ...................................... 280
C Master Mode (7 or 10-bit Transmission) ............ 156
C Master Mode (7-bit Reception) .......................... 157
C Slave Mode (10-bit Transmission) ..................... 143
C Slave Mode (7-bit Transmission) ....................... 141
C Slave Mode with SEN = 0
C Slave Mode with SEN = 0
C Slave Mode with SEN = 1
C Slave Mode with SEN = 1
(10-bit Reception) ............................................ 142
(7-bit Reception) .............................................. 140
(10-bit Reception) ............................................ 147
(7-bit Reception) .............................................. 146
Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 272
(7 or 10-bit Address Mode) .............................. 148
(MCLR Tied to V
(MCLR Not Tied to V
Case 1 ............................................................... 30
Case 2 ............................................................... 30
(MCLR Tied to V
(Master/Slave) ................................................. 284
2
2
2
C Bus Data ........................................ 282
C Bus START/STOP Bits .................. 282
C Bus START/STOP Bits .................. 282
PIC18FXX39
DD
DD
) .......................................... 31
) .......................................... 30
DD
)
DD
DS30485A-page 315
) ......................... 31