PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 223

IC MCU FLASH 12KX16 EE A/D 28DIP

PIC18F2539-I/SP

Manufacturer Part Number
PIC18F2539-I/SP
Description
IC MCU FLASH 12KX16 EE A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2539-I/SP

Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
21
Eeprom Memory Size
256Byte
Ram Memory Size
1.375KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
 Details
BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2002 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Carry
If Carry
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ‘0’
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
0011
BNC
operation
Process
Process
Data
Data
No
Q3
Q3
n
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
Preliminary
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Negative
If Negative
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
[ label ] BNN
-128 ≤ n ≤ 127
if negative bit is ‘0’
(PC) + 2 + 2n → PC
None
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
PIC18FXX39
'n'
'n'
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
0111
BNN
operation
Process
Process
Data
Data
No
Q3
Q3
n
DS30485A-page 221
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn

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