PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 164

• Manufacturer Part Number: PIC18F2539-I/SP
• Description: IC MCU FLASH 12KX16 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2539-I/SP

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.375KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Details

PIC18FXX39
16.4.17.2
During a Repeated START condition, a bus collision
occurs if:
a)
b)
When the user de-asserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to ‘0’. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master
Figure 16-29). If SDA is sampled high, the BRG is
FIGURE 16-29:
FIGURE 16-30:
DS30485A-page 162
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to
transmit a data ‘1’.
is
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
attempting
Bus Collision During a Repeated
START Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
to
transmit
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
a
data
Preliminary
’0’,
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated START
condition, see Figure 16-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
T
Cleared in software
 2002 Microchip Technology Inc.
BRG
Interrupt cleared
in software
'0'
'0'
'0'