DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 101

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

FIGURE 15-4:
15.8
An Independent PWM Output mode is required for
driving certain types of loads. A particular PWM output
pair is in the Independent Output mode when the
corresponding PMOD bit in the PWMCON1 register is
set. No dead-time control is implemented between
adjacent PWM I/O pins when the module is operating
in the Independent mode and both I/O pins are allowed
to be active simultaneously.
In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output
pair. By using the associated Duty Cycle register and
the appropriate bits in the OVDCON register, the user
may select the following signal output options for each
PWM I/O pin operating in the Independent mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
15.9
The PWM module produces single-pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only
edge-aligned outputs may be produced in the
Single-Pulse mode. In Single-Pulse mode, the PWM
I/O pin(s) are driven to the active state when the PTEN
bit is set. When a match with a Duty Cycle register
occurs, the PWM I/O pin is driven to the inactive state.
When a match with the PTPER register occurs, the
PTMR register is cleared, all active PWM I/O pins are
driven to the inactive state, the PTEN bit is cleared and
an interrupt is generated.
© 2008 Microchip Technology Inc.
PWMxH
Time selected by DTSxA bit (A or B)
Duty Cycle Generator
PWMxL
Independent PWM Output
Single-Pulse PWM Operation
DEAD-TIME TIMING DIAGRAM
15.10 PWM Output Override
The PWM output override bits allow the user to
manually drive the PWM I/O pins to specified logic
states, independent of the duty cycle comparison units.
All control bits associated with the PWM output
override function are contained in the OVDCON
register. The upper half of the OVDCON register
contains eight bits, POVDxH<4:1> and POVDxL<4:1>,
that determine which PWM I/O pins will be overridden.
The lower half of the OVDCON register contains eight
bits, POUTxH<4:1> and POUTxL<4:1>, that determine
the state of the PWM I/O pins when a particular output
is overridden via the POVD bits.
15.10.1
When a PWMxL pin is driven active via the OVDCON
register, the output signal is forced to be the
complement of the corresponding PWMxH pin in the
pair. Dead-time insertion is still performed when PWM
channels are overridden manually.
15.10.2
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time base. Synchronous
output overrides occur at the following times:
• Edge-Aligned mode, when PTMR is zero.
• Center-Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
dsPIC30F5015/5016
COMPLEMENTARY OUTPUT MODE
OVERRIDE SYNCHRONIZATION
Time selected by DTSxI bit (A or B)
DS70149D-page 101