DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 37

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

4.0
The dsPIC DSC core contains two independent
Address Generator Units (AGU): the X AGU and Y
AGU. The Y AGU supports word-sized data reads for
the DSP MAC class of instructions only. The dsPIC DSC
AGUs support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
© 2008 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
Note:
ADDRESS GENERATOR UNITS
Instruction Addressing Modes
Addressing Mode
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
FUNDAMENTAL ADDRESSING MODES SUPPORTED
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and a literal forms the EA.
4.1.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192 bytes
of data memory (near data space). Most file register
instructions employ a working register W0, which is
denoted as WREG in these instructions. The destination
is typically either the same file register, or WREG (with
the exception of the MUL instruction), which writes the
result to a register or register pair. The MOV instruction
allows additional flexibility and can access the entire
data space during file register operation.
4.1.2
The three-operand MCU instructions are of the form:
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location.
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
dsPIC30F5015/5016
Operand 3 = Operand 1 <function> Operand 2
Description
The
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
following
addressing
DS70149D-page 37
modes
are