ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 171

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
ICi Rregister is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0] (see
– Select the edge of the active transition on the
And select the following in the CR1/CR3 register:
– To enable both ICAP1 & ICAP2 interrupts, set
ICAP2 pin with the IEDG2 bit, if ICAP2 is active.
the ICIE bit in the CR1 register (in this case, the
IC1IE & IC2IE enable bits are not significant).
To enable only one ICAP interrupt, reset the ICIE
bit and set the IC1IE (or IC2IE) bit.
Note: If ICIE is reset and both IC1IE & IC2IE are
set, both interrupts are enabled.
In all cases, set the EFTIS bit to enable timer in-
terrupts globally
ICiR
INTCLK /CC[1:0]
MS Byte
ICiHR
).
LS Byte
ICiLR
Table
36).
– Select the edge of the active transition on the
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
– A timer interrupt is generated under the following
Clearing the Input Capture interrupt request is
done by:
1. An access (read or write) to the SR register
2. An access (read or write) to the ICiLR register.
Note: After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
ICAP1 pin with the IEDG1 bit if ICAP1 is active.
running counter on the active transition on the
ICAPi pin (see
two conditions :
1. If the ICIE bit (for both ICAP1 & ICAP2) and
2. If the ICIE bit is reset and the IC1IE and /or
while the ICFi bit is set.
the EFTIS bit are set.
Note: If the ICIE bit is set, the status of the
IC1IE/IC2IE bits in the CR3 register is not sig-
nificant.
IC2IE bits are set and the EFTIS bit is set.
Otherwise, the interrupt remains pending until
the related enable bits are set.
EXTENDED FUNCTION TIMER (EFT)
Figure
96).
171/429
9