ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 395

MCU 8BIT 128K FLASH 100PQFP

ST92F150CV1QB

Manufacturer Part Number
ST92F150CV1QB
Description
MCU 8BIT 128K FLASH 100PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet

Specifications of ST92F150CV1QB

Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-QFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
5 x 16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4882

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SPI TIMING TABLE
(V
Note:
Measurement points are V
(1) Values guaranteed by design.
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
N° Symbol
10
11
12
13
1
2
3
4
5
6
7
8
9
DD
= 5V ± 10%, T
t
t
t
SPI_H
SPI_L
t
t
f
t
t
t
Lead
t
t
Hold
Rise
Lag
SPI
SPI
Fall
SU
t
t
Dis
t
H
A
V
SPI frequency
SPI clock period
Enable lead time
Enable lag time
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
Data hold time (inputs)
Access time (time to data active
from high impedance state)
Disable time (hold time to high im-
pedance state)
Data valid
Data hold time (outputs)
Rise time
(20% V
Fall time
(70% V
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
A
OL
DD
DD
=
, V
to 70% V
to 20% V
OH
Parameter
40°C to +125°C, C
, V
IL
and V
DD
DD
, C
, C
IH
L
L
in the SPI Timing Diagram.
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
= 200pF)
= 200pF)
Load
Master
Slave
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Master (before capture edge)
Slave (after enable edge)
Master (before capture edge)
Slave (after enable edge)
Outputs: SCK,MOSI,MISO
Inputs: SCK,MOSI,MISO,SS
Outputs: SCK,MOSI,MISO
Inputs: SCK,MOSI,MISO,SS
= 50pF, f
Condition
INTCLK
= 24MHz, unless otherwise specified)
f
INTCLK
4 x Tck
2 x Tck
Tck / 4
Tck / 4
Min
40
40
80
90
80
90
40
40
40
40
0
0
0
/ 128
Value
(1)
f
f
INTCLK
INTCLK
Max
120
240
120
100
100
100
100
/ 4
/ 2
395/429
MHz
Unit
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1

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