ST92F150CV1QB STMicroelectronics, ST92F150CV1QB Datasheet - Page 186

• Manufacturer Part Number: ST92F150CV1QB
• Description: MCU 8BIT 128K FLASH 100PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1QB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4882

EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
STATUS REGISTER (SR)
R254 - Read Only
Register Page: 28
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
Bit 5 = TOF Timer Overflow.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
Bit 2:0 = Reserved, forced by hardware to 0.
186/429
9
ICF1
first read the SR register, then read or write the
low byte of the IC1R (IC1LR) register.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
7
OCF1
TOF
ICF2
OCF2
0
0
0
0
CONTROL REGISTER 3 (CR3)
R255 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Bit 7 = IC1IE Input Capture1 interrupt enable
This bit is not significant if the ICIE bit in the CR1
register is set.
0: ICAP1 interrupt disabled
1: ICAP1 interrupt enabled
Bit 6 = OC1IE output compare 1 interrupt enable
This bit is not significant if the OCIE bit in the CR1
register is set.
0: OCMP1 interrupt disabled
1: OCMP1 interrupt enabled
Bit 5 = IC2IE input capture 2 interrupt enable
This bit is not significant if the ICIE bit in the CR1
register is set.
0: ICAP2 interrupt disabled
1: ICAP2 interrupt enabled
Bit 4= OC2IE output compare 2 interrupt enable
This bit is not significant if the OCIE bit in the CR1
register is set.
0: OCMP2 interrupt disabled
1: OCMP2 interrupt enabled
Bits 3:1 = Reserved, must be kept cleared.
Bit 0 = EFTIS Global Timer Interrupt Selection.
0: Select External interrupt.
1: Select Global Timer Interrupt.
IC1IE OC1IE IC2IE OC2IE
7
0
0
0
EFTIS
0