MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 182
![MCU 8BIT 16K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM16CGT
Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM16CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08JM16CGT
Manufacturer:
PIXART
Quantity:
1 001
Part Number:
MC9S08JM16CGT
Manufacturer:
FREESCALE
Quantity:
20 000
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Multi-Purpose Clock Generator (S08MCGV1)
12.3
12.3.1
182
IREFSTEN
IRCLKEN
IREFS
CLKS
Field
RDIV
7:6
5:3
2
1
0
Reset:
Register Definition
W
R
MCG Control Register 1 (MCGC1)
Clock Source Select — Selects the system clock source.
00
01
10
11
Reference Divider — Selects the amount to divide down the reference clock selected by the IREFS bit. If the
FLL is selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected,
the resulting frequency must be in the range 1 MHz to 2 MHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128
Internal Reference Select — Selects the reference clock source.
1 Internal reference clock selected
0 External reference clock selected
Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
1 MCGIRCLK active
0 MCGIRCLK inactive
Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
0 Internal reference clock is disabled in stop
entering stop
Encoding 0 — Output of FLL or PLL is selected.
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Encoding 3 — Reserved, defaults to 00.
7
0
CLKS
Table 12-1. MCG Control Register 1 Field Descriptions
Figure 12-3. MCG Control Register 1 (MCGC1)
0
6
MC9S08JM16 Series Data Sheet, Rev. 2
0
5
RDIV
0
4
Description
0
3
IREFS
1
2
IRCLKEN
Freescale Semiconductor
0
1
IREFSTEN
0
0
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