MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 34

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Modes of Operation
For the ACMP to operate when ACGBS in ACMPSC is set, the LVD must be left enabled when entering
stop3.
For the XOSC to operate with an external reference when RANGE in MCGC2 is set, the LVD must be left
enabled when entering stop3.
3.6.1.2
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. If the user
attempts to enter stop2 with ENBDM set, the MCU will enter stop3 instead.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
of the internal circuitry of the MCU is powered off in stop2, with the exception of the RAM. Upon entering
stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting either wake-up pin: RESET or IRQ.
In addition, the RTC interrupt can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
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All module control and status registers are reset
The LVD reset function is enabled and the MCU remains in the reset state if V
trip point (low trip point selected due to POR)
The CPU takes the reset vector
Stop2 Mode
Active BDM Enabled in Stop Mode
IRQ/TPMCLK always functions as an active-low wakeup input when the
MCU is in stop2, regardless of how the pin is configured before entering
stop2. The pullup on this pin is always disabled in stop2. This pin must be
driven or pulled high externally while in stop2 mode.
Chapter 18, “Development
MC9S08JM16 Series Data Sheet, Rev. 2
NOTE
Support.” If ENBDM is set when the CPU executes a
Freescale Semiconductor
DD
is below the LVD
Table
3-1. Most