MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 263
![MCU 8BIT 16K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM16CGT
Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM16CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08JM16CGT
Manufacturer:
PIXART
Quantity:
1 001
Part Number:
MC9S08JM16CGT
Manufacturer:
FREESCALE
Quantity:
20 000
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15.5
15.5.1
15.5.1.1
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
15.5.1.2
In this example, the SPI module will be set up for master mode with only hardware match interrupts
enabled. The SPI will run in 16-bit mode at a maximum baud rate of bus clock divided by 2. Clock phase
and polarity will be set for an active-high SPI clock where the first edge on SPSCK occurs at the start of
the first cycle of a data transfer.
Freescale Semiconductor
SPIxC1=0x54(%01010100)
1. Update control register 1 (SPIxC1) to enable the SPI and to control interrupt enables. This register
2. Update control register 2 (SPIxC2) to enable additional SPI functions such as the SPI match
3. Update the baud rate register (SPIxBR) to set the prescaler and bit rate divisor for an SPI master.
4. Update the hardware match register (SPIxMH:SPIxML) with the value to be compared to the
5. In the master, read SPIxS while SPTEF = 1, and then write to the transmit data register
also sets the SPI as master or slave, determines clock phase and polarity, and configures the main
SPI options.
interrupt feature, the master mode-fault function, and bidirectional mode output. 8- or 16-bit mode
select and other optional features are controlled here as well.
receive data register for triggering an interrupt if hardware match interrupts are enabled.
(SPIxDH:SPIxDL) to begin transfer.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Initialization/Application Information
SPI Module Initialization Example
Initialization Sequence
Pseudo—Code Example
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 0
MC9S08JM16 Series Data Sheet, Rev. 2
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
Serial Peripheral Interface (S08SPI16V1)
263
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