MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 80
![MCU 8BIT 16K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM16CGT
Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM16CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08JM16CGT
Manufacturer:
PIXART
Quantity:
1 001
Part Number:
MC9S08JM16CGT
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 6 Parallel Input/Output
6.5
This section provides information about the registers associated with the parallel I/O ports and pin control
functions. These parallel I/O registers are located in page zero of the memory map and the pin control
registers are located in the high page register section of memory.
Refer to tables in
control registers. This section refers to registers and control bits only by their names. A Freescale-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.5.1
Port A parallel I/O function is controlled by the registers listed below.
80
PTADD[5,0]
PTAD[5,0]
Reset
Reset
Field
Field
5,0
5,0
W
W
R
R
Parallel I/O and Pin Control Registers
Port A I/O Registers (PTAD and PTADD)
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
0
0
7
7
Chapter 4,
Figure 6-3. Data Direction for Port A Register (PTADD)
0
0
6
6
“Memory,” for the absolute address assignments for all parallel I/O and pin
Table 6-2. PTADD Register Field Descriptions
Table 6-1. PTAD Register Field Descriptions
Figure 6-2. Port A Data Register (PTAD)
PTADD5
MC9S08JM16 Series Data Sheet, Rev. 2
PTAD5
0
0
5
5
0
0
4
4
Description
Description
3
0
3
0
0
0
2
2
Freescale Semiconductor
0
0
1
1
PTADD0
PTAD0
0
0
0
0
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