MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 253
![MCU 8BIT 16K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM16CGT
Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM16CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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and SPSCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and
also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs
are disabled and SPSCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPIxS). If the SPI
interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also
requested.
When a write to the SPI Data Register in the master occurs, there is a half SPSCK-cycle delay. After the
delay, SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on
the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see
“SPI Clock
15.4.3
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.
In slave mode, SPSCK is the SPI clock input from the master.
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is
determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2.
be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle
state.
is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data
output pin. Also, if the slave is not selected (SS is high), then the SPSCK input is ignored and no internal
shifting of the SPI shift register takes place.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI
data in a slave mode. For these simpler devices, there is no serial data out pin.
Freescale Semiconductor
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must
•
•
•
SPSCK
MISO, MOSI pin
SS pin
Formats.”)
Slave Mode
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0,
BIDIROE with SPC0 set, SPIMODE, SPPR2–SPPR0 and SPR2–SPR0 in
master mode will abort a transmission in progress and force the SPI into idle
state. The remote slave cannot detect this, therefore the master has to ensure
that the remote slave is set back to idle state.
MC9S08JM16 Series Data Sheet, Rev. 2
NOTE
Serial Peripheral Interface (S08SPI16V1)
Section 15.4.5,
253
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