MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 132
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MCHC908JW32FAE
Manufacturer Part Number
MCHC908JW32FAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.RD3152MMA7260Q.pdf
(232 pages)
Specifications of MCHC908JW32FAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908JW32FAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCHC908JW32FAE
Manufacturer:
FREESCALE
Quantity:
20 000
Serial Peripheral Interface Module (SPI)
10.5.3 Transmission Format When CPHA = 1
Figure 10-6
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
10.7.2 Mode Fault
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
10.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since
the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower
SPSCK. This uncertainty causes the variation in the initiation delay shown in
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
132
shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a
CAPTURE STROBE
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
SPSCK CYCLE #
FROM MASTER
SS
FROM SLAVE
;
Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
TO SLAVE
MOSI
MISO
Figure 10-6. Transmission Format (CPHA = 1)
MSB
MC68HC908JW32 Data Sheet, Rev. 6
MSB
1
Figure
BIT 6
BIT 6
2
10-7.) The internal SPI clock in the master is a free-running
BIT 5
BIT 5
3
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Figure
LSB
8
Freescale Semiconductor
LSB
10-7. This delay is