MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 82

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of
4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
6.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter.
free-running after all reset states.
internal reset recovery sequences.)
6.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
6.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing, and
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
82
INTERRUPT
INTERRUPT
•
•
•
MODULE
MODULE
I-BIT
I-BIT
Interrupts:
–
–
Reset
Break interrupts
R/W
R/W
IAB
IDB
IAB
IDB
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
DUMMY
DUMMY
Figure 6-9
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
Figure 6-9. Interrupt Recovery Timing
CCR
(See 6.3.2 Active Resets from Internal Sources
Figure 6-8. Interrupt Entry Timing
MC68HC908JW32 Data Sheet, Rev. 6
SP – 1
SP – 3
shows interrupt recovery timing.
A
SP – 2
SP – 2
(See 6.6.2 Stop Mode
X
X
SP – 3
SP – 1
PC – 1[15:8] PC – 1[7:0]
A
SP – 4
SP
CCR
VECT H
PC
for details.) The SIM counter is
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
for counter control and
Figure 6-8
Freescale Semiconductor
START ADDR
OPCODE
shows