MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 160
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MCHC908JW32FAE
Manufacturer Part Number
MCHC908JW32FAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.RD3152MMA7260Q.pdf
(232 pages)
Specifications of MCHC908JW32FAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
HC08JW
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USB
Number Of Programmable I/os
29
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908JW32FAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCHC908JW32FAE
Manufacturer:
FREESCALE
Quantity:
20 000
USB 2.0 FS Module
SIZE[1:0] — Buffer size Selection bits
DIR — Endpoint Direction Bit
STALL — Forced STALL Handshake Enable
MODE[1:0] — Endpoint Type selection
160
This read/write bits select the buffer size for the corresponding endpoint. When USBEN is set, these
bits has no effect.
TFRCIE — Transfer Complete Interrupt Enable
This read/write bit enables the CPU interrupt associated with the TFRC flag.
Setting this bit enables the endpoint to become IN endpoint. Clearing this bit enables the endpoint to
become OUT endpoint. Writing to this bit will have no effect when USBEN is set.
This read/write bit causes endpoint 0 to return a STALL handshake when polled by either an IN or OUT
token by the USB host. If the bit is set by software, when a data packet addressed to that endpoint is
detected, this STALL status will be latched to the module, the bit is cleared automatically and the
packet will be responded by STALL. Once the STALL status is latched, it can only be cleared by
CLEAR_FEATURE command from the host. Software cannot clear this status. If there is no packet
addressed to the endpoint after the bit is set, it can still be cleared by writing zero. Reset clears this bit.
This bit selects the type of the endpoint. When USBEN is set, this bit has no effect.
1 = TFRC flag interrupt is enabled
0 = TFRC flag interrupt is disabled
1 = IN endpoint is enabled
0 = OUT endpoint is enabled
1 = Send STALL handshake
0 = Do not response STALL handshaking
When USB RESET is detected, explicitly writing zero to the STALL bit is
recommended to ensure all unlatched STALL status is cleared.
Table 11-5. Mode selection for Endpoint type
Table 11-4. Buffer Size Selection Table
MODE[1:0]
MC68HC908JW32 Data Sheet, Rev. 6
SIZE[1:0]
00
01
10
11
00
01
10
11
NOTE
Endpoint Disable
Endpoint Type
Interrupt
Buffer Size
Bulk
16 Bytes
32 Bytes
64 Bytes
—
8 Bytes
Freescale Semiconductor