MCHC908JW32FAE Freescale Semiconductor, MCHC908JW32FAE Datasheet - Page 176

• Manufacturer Part Number: MCHC908JW32FAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Input/Output (I/O) Ports
13.5 Port D
Port D is a 8-bit general-purpose bidirectional I/O port.
13.5.1 Port D Data Register
The port D data register contains a data latch for each of the eight port D pins.
PTD[7:0] — Port D Data Bits
PTD2, PTD3 and PTD7
13.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
176
These read/write bits are software programmable. Data direction of each port D pin is under control of
the corresponding bit in data direction register D. Reset has no effect on port D data.
There is programmable pullup associated with the pins. The pullup are default enabled and can be
controlled via POCR2 register.
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Additional Function:
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
Address:
Reset:
Read:
Write:
DDRD7
$0007
Bit 7
0
Optional
$0003
Pullup
PTD7
Bit 7
Figure 13-12. Data Direction Register D (DDRD)
Figure 13-11. Port D Data Register (PTD)
DDRD6
= Unimplemented
6
0
PTD6
MC68HC908JW32 Data Sheet, Rev. 6
6
DDRD5
5
0
PTD5
5
NOTE
DDRD4
4
0
Unaffected by reset
PTD4
4
DDRD3
3
0
Optional
Pullup
PTD3
3
DDRD2
2
0
Optional
Pullup
PTD2
2
DDRD1
1
0
PTD1
1
Freescale Semiconductor
DDRD0
Bit 0
0
PTD0
Bit 0