MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 132
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 6 Parallel Input/Output Control
6.5.9
Port J is controlled by the registers listed below.
6.5.9.1
6.5.9.2
132
PTJDD[7:0]
PTJD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTJDD7
PTJD7
Port J Registers
Port J Data Register Bits — For port J pins that are inputs, reads return the logic level on the pin. For port J
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port J pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTJD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port J Bits — These read/write bits control the direction of port J pins and what is read for
PTJD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port J bit n and PTJD reads return the contents of PTJDn.
Port J Data Register (PTJD)
0
Port J Data Direction Register (PTJDD)
0
7
7
PTJDD6
PTJD6
0
0
6
6
Figure 6-53. Port J Data Direction Register (PTJDD)
Table 6-51. PTJDD Register Field Descriptions
Table 6-50. PTJD Register Field Descriptions
Figure 6-52. Port J Data Register (PTJD)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTJDD5
PTJD5
0
0
5
5
PTJDD4
PTJD4
0
0
4
4
Description
Description
PTJDD3
PTJD3
3
0
3
0
PTJDD2
PTJD2
0
0
2
2
PTJDD1
Freescale Semiconductor
PTJD1
0
0
1
1
PTJDD0
PTJD0
0
0
0
0
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