MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 404
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 18 Debug Module (S08DBGV3) (128K)
18.3.3.11 Debug Comparator C Extension Register (DBGCCX)
1
404
end-run
Module Base + 0x000A
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
PAGSEL
RWCEN
Reset
Bit 16
Field
RWC
POR
7
6
5
0
W
R
1
RWCEN
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for Comparator C.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
Comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Comparator C Page Select Bit — This PAGSEL bit controls whether Comparator C will be qualified with the
internal signal (mmu_papge_sel) that indicates an extended access through the PPAGE mechanism. When
mmu_ppage_sel = 1, the 17-bit core address is a paged program access, and the 17-bit core address is made
up of PPAGE[2:0]:addr[13:0]. When mmu_papge_sel = 0, the 17-bit core address is either a 16-bit CPU address
with a leading 0 in bit 16, or a 17-bit linear address pointer value.
0 Match qualified by mmu_ppage_sel = 0 so address bits [16:0] correspond to a 17-bit CPU address with a
1 Match qualified by mmu_ppage_sel = 1 so address bits [16:0] compare to flash memory address made up of
Comparator C Extended Address Bit 16 Compare Bit — The Comparator C bit 16 compare bit controls
whether Comparator C will compare the core address bus bit 16 to a logic 1 or logic 0.
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
U
0
7
leading zero at bit 16, or a 17-bit linear address pointer address
PPAGE[2:0]:addr[13:0]
Figure 18-12. Debug Comparator C Extension Register (DBGCCX)
= Unimplemented or Reserved
RWC
U
0
6
Table 18-13. DBGCCX Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PAGSEL
U
0
5
0
0
0
4
Description
0
0
0
3
0
0
0
2
Freescale Semiconductor
0
0
0
1
Bit 16
U
0
0
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