MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 170
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
8.3
8.3.1
170
IREFSTEN
IRCLKEN
IREFS
CLKS
Field
RDIV
7:6
5:3
2
1
0
Reset:
Register Definition
W
R
MCG Control Register 1 (MCGC1)
Clock Source Select — Selects the system clock source.
00
01
10
11
External Reference Divider — Selects the amount to divide down the external reference clock. If the FLL is
selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the
resulting frequency must be in the range 1 MHz to 2 MHz. See
Internal Reference Select — Selects the reference clock source.
1 Internal reference clock selected
0 External reference clock selected
Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
1 MCGIRCLK active
0 MCGIRCLK inactive
Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
0 Internal reference clock is disabled in stop
entering stop
Encoding 0 — Output of FLL or PLL is selected.
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Encoding 3 — Reserved, defaults to 00.
7
0
CLKS
Table 8-1. MCG Control Register 1 Field Descriptions
0
6
Figure 8-3. MCG Control Register 1 (MCGC1)
MC9S08DZ128 Series Data Sheet, Rev. 1
0
5
RDIV
0
4
Description
0
3
Table 8-2
IREFS
and
1
2
Table 8-3
IRCLKEN
Freescale Semiconductor
for the divide-by factors.
0
1
IREFSTEN
0
0
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