MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 413
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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end the trace run that was in progress. The ARMF bit is also cleared if ARM is written to zero or when the
DBGEN bit is low. The TBC logic determines whether a trigger condition has been met based on the
trigger mode and the trigger selection.
18.4.4.3
The on-chip ICE system supports nine trigger modes. The trigger modes are encoded as shown in
Table
FIFO. When the match condition is met, the appropriate flag AF or BF is set in DBGS register. Arming
the DBG module clears the AF, BF, and CF flags in the DBGS register. In all trigger modes except for the
event only modes change of flow addresses are stored in the FIFO. In the event only modes only the value
on the data bus at the trigger event B comparator match address will be stored.
18.4.4.3.1
In the A Only trigger mode, if the match condition for A is met, the AF flag in the DBGS register is set.
18.4.4.3.2
In the A Or B trigger mode, if the match condition for A or B is met, the corresponding flag(s) in the DBGS
register are set.
18.4.4.3.3
In the A Then B trigger mode, the match condition for A must be met before the match condition for B is
compared. When the match condition for A or B is met, the corresponding flag in the DBGS register is set.
18.4.4.3.4
In the Event Only B trigger mode, if the match condition for B is met, the BF flag in the DBGS register is
set. The Event Only B trigger mode is considered a begin-trigger type and the BEGIN bit in the DBGT
register is ignored.
18.4.4.3.5
In the A Then Event Only B trigger mode, the match condition for A must be met before the match
condition for B is compared. When the match condition for A or B is met, the corresponding flag in the
DBGS register is set. The A Then Event Only B trigger mode is considered a begin-trigger type and the
BEGIN bit in the DBGT register is ignored.
18.4.4.3.6
In the A And B trigger mode, Comparator A compares to the address bus and Comparator B compares to
the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle,
both the AF and BF flags in the DBGS register are set. If a match condition on only A or only B happens,
no flags are set.
For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be
used to determine if the Breakpoint conditions are met and Comparator B matches will be ignored.
Freescale Semiconductor
18-17. The trigger mode is used as a qualifier for either starting or ending the storing of data in the
Trigger Modes
A Only
A Or B
A Then B
Event Only B
A Then Event Only B
A And B (Full Mode)
MC9S08DZ128 Series Data Sheet, Rev. 1
Chapter 18 Debug Module (S08DBGV3) (128K)
413
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