M37542F8FP#W4 Renesas Electronics America, M37542F8FP#W4 Datasheet - Page 34

• Manufacturer Part Number: M37542F8FP#W4
• Description: IC 740 MCU FLASH 32K 36-SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#W4

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7542 Group
Rev.3.03
REJ03B0006-0303
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P1
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR
When the CNTR
by the timer X count source selection bit is counted while the input
signal level of CNTR
pin is “L”. Also, when the CNTR
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
(1) CNTR
CNTR
switch bit.
When this bit is “0”, the CNTR
the falling edge of CNTR
CNTR
CNTR
(2) CNTR
According to the setting value of CNTR
the interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Note on Timer X
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the active edge switch bit.
Set the corresponding interrupt enable bit to “1” (enabled).
0
0
0
interrupt active edge depends on the CNTR
pin input signal.
interrupt request bit is set to “1” at the rising edge of
0
0
interrupt active edge selection-1
interrupt active edge selection-2
Jul 11, 2008
4
/CNTR
0
active edge switch bit is “0”, the signal selected
0
0
pin is “H”. The count is stopped while the
pin is measured.
0
0
pin.
pin input signal. When this bit is “1”, the
0
interrupt request bit is set to “1” at
Page 32 of 117
0
active edge switch bit is “1”, the
0
active edge switch bit,
0
pin is “L”. The count
0
active edge
Fig. 29 Structure of timer X mode register
Fig. 30 Timer count source set register
Notes 1: f(X
b 7
b7
2: On-chip oscillator can be used when the on-chip oscillator
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
is enabled by bit 3 of CPUM.
IN
) can be used as timer X count source when using
b 0
b0
T i m e r X m o d e r e g i s t e r
( T X M : a d d r e s s 0 0 2 B
Timer count source set register
(TCSS : address 002A
Timer A count source selection bits
Timer X count source selection bits
Timer B count source selection bits
T i m e r X o p e r a t i n g m o d e b i t s
C N T R
T i m e r X c o u n t s t o p b i t
P 0
N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )
b4 b3 b2
0
0
0
0
1
1
1
1
b1 b0
0
0
1
1
b7 b6 b5
b 1 b 0
0
0
1
1
0 : I n t e r r u p t a t f a l l i n g e d g e
1 : I n t e r r u p t a t r i s i n g e d g e
0 : C o u n t s t a r t
1 : C o u n t s t o p
0 : O u t p u t i n v a l i d ( I / O p o r t )
1 : O u t p u t v a l i d ( I n v e r t e d C N T R
0
0
0
0
1
1
1
1
3
/ T X
0
0
1
1
0
0
1
1
0 : f(X
1 : f(X
0 : f(X
1 : Not available
0
0
1
1
0
0
1
1
0 : T i m e r m o d e
1 : P u l s e o u t p u t m o d e
0 : E v e n t c o u n t e r m o d e
1 : P u l s e w i d t h m e a s u r e m e n t m o d e
0
C o u n t a t r i s i n g e d g e
( i n e v e n t c o u n t e r m o d e )
C o u n t a t f a l l i n g e d g e
( i n e v e n t c o u n t e r m o d e )
O U T
a c t i v e e d g e s w i t c h b i t
0 : f(X
1 : f(X
0 : f(X
1 : f(X
0 : f(X
1 : f(X
0 : On-chip oscillator output (Note 2)
1 : Not available
0 : f(X
1 : f(X
0 : f(X
1 : f(X
0 : f(X
1 : f(X
0 : Timer A underflow
1 : Not available
IN
IN
IN
o u t p u t v a l i d b i t
)/16
)/2
) (Note 1)
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
)/16
)/2
)/32
)/64
)/128
)/256
)/16
)/2
)/32
)/64
)/128
)/256
16
1 6
, initial value: 00
, i n i t i a l v a l u e : 0 0
0
o u t p u t )
16
1 6
)
)