M37542F8FP#W4 Renesas Electronics America, M37542F8FP#W4 Datasheet - Page 50

• Manufacturer Part Number: M37542F8FP#W4
• Description: IC 740 MCU FLASH 32K 36-SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#W4

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7542 Group
(2) Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Fig. 57 Block diagram of UART serial I/O1
Rev.3.03
REJ03B0006-0303
Fig. 58 Operation of UART serial I/O1 function
Transmit or receive clock
P 1
0
/ R
P 1
P1
Serial output T
Serial input R
X
Transmit buffer 1
Notes
2
Receive buffer 1
D
1
/ S
/T
1
/ C A P
C L K 1
write signal
X
read signal
X
Jul 11, 2008
D
I N
1
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
0
interrupt source selection bit (TIC) of the serial I/O1 control register.
X
X
D
D
1
1
ST detector
B R G c o u n t s o u r c e s e l e c t i o n b i t
TBE=0
1/4
Character length selection bit
TSC=0
TBE=1
C h a r a c t e r l e n g t h s e l e c t i o n b i t
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ST
8 b i t s
ST
7 b i t s
S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t
OE
D
D
0
A d d r e s s 0 0 1 8
0
TBE=0
PE FE
D
D
R e c e i v e s h i f t r e g i s t e r 1
R e c e i v e b u f f e r r e g i s t e r 1
1
1
F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 )
S T / S P / P A g e n e r a t o r
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
D a t a b u s
Baud rate generator 1
Data bus
1 6
Transmit buffer register 1
T r a n s m i t s h i f t r e g i s t e r 1
SP detector
A d d r e s s 0 0 1 C
Address
S e r i a l I / O 1 c o n t r o l r e g i s t e r
1 / 1 6
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
1 6
C l o c k c o n t r o l c i r c u i t
0018
RBF=1
SP
SP
TBE=1
16
R e c e i v e b u f f e r f u l l f l a g ( R B F )
R e c e i v e i n t e r r u p t r e q u e s t ( R I )
Transmit interrupt source selection bit
ST
ST
Serial I/O1 status register
D
0
D
0
A d d r e s s 0 0 1 A
RBF=0
1/16
D
D
1
1
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
Transmit shift completion flag (TSC)
U A R T 1 c o n t r o l r e g i s t e r
Generated at 2nd bit in 2-stop-bit mode
T r a n s m i t i n t e r r u p t r e q u e s t ( T I )
1 6
Address
Address 001B
0019
16
16
SP
TSC=1
RBF=1
SP