HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet
HD64F3672FPIV
Specifications of HD64F3672FPIV
Related parts for HD64F3672FPIV
HD64F3672FPIV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3672 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked ...
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Rev.4.00 Nov. 02, 2005 Page ii of xxiv ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/3672 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...
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When the used, NMI is an input/output pin (open-drain in output mode). Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of ...
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Rev.4.00 Nov. 02, 2005 Page viii of xxiv ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram.......................................................................................................... 2 1.3 Pin Arrangement .................................................................................................................... 3 1.4 Pin Functions ......................................................................................................................... 5 Section 2 CPU........................................................................................................7 2.1 Address Space and Memory Map .......................................................................................... 8 2.2 Register Configuration........................................................................................................... 9 2.2.1 General Registers.................................................................................................... 10 ...
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Wakeup Interrupt Flag Register (IWPR) ................................................................ 47 3.3 Reset Exception Handling.................................................................................................... 48 3.4 Interrupt Exception Handling .............................................................................................. 48 3.4.1 External Interrupts .................................................................................................. 48 3.4.2 Internal Interrupts ................................................................................................... 49 3.4.3 Interrupt Handling Sequence .................................................................................. 50 3.4.4 Interrupt Response Time......................................................................................... 51 ...
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Subsleep Mode........................................................................................................ 76 6.3 Operating Frequency in Active Mode.................................................................................. 77 6.4 Direct Transition .................................................................................................................. 77 6.5 Module Standby Function.................................................................................................... 77 Section 7 ROM ....................................................................................................79 7.1 Block Configuration............................................................................................................. 79 7.2 Register Descriptions ........................................................................................................... 80 7.2.1 Flash Memory Control Register 1 ...
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Port Data Register 5 (PDR5) ................................................................................ 104 9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 105 9.3.5 Pin Functions ........................................................................................................ 105 9.4 Port 7.................................................................................................................................. 107 9.4.1 Port Control Register 7 (PCR7) ............................................................................ 108 9.4.2 Port Data Register 7 (PDR7) ................................................................................ ...
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Timer Counter (TCNT)......................................................................................... 141 11.3.8 General Registers (GRA to GRD)............................................................. 141 11.4 Operation ........................................................................................................................... 142 11.4.1 Normal Operation ................................................................................................. 142 11.4.2 PWM Operation.................................................................................................... 146 11.5 Operation Timing............................................................................................................... 151 11.5.1 TCNT Count Timing ............................................................................................ 151 11.5.2 Output ...
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Serial Data Reception ........................................................................................... 181 13.5 Operation in Clocked Synchronous Mode ......................................................................... 185 13.5.1 Clock..................................................................................................................... 185 13.5.2 SCI3 Initialization................................................................................................. 185 13.5.3 Serial Data Transmission ...................................................................................... 186 13.5.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 189 13.5.5 Simultaneous Serial Data ...
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Section 16 List of Registers ...............................................................................217 16.1 Register Addresses (Address Order).................................................................................. 218 16.2 Register Bits....................................................................................................................... 221 16.3 Register States in Each Operating Mode ........................................................................... 224 Section 17 Electrical Characteristics .................................................................227 17.1 Absolute Maximum Ratings .............................................................................................. 227 17.2 Electrical Characteristics.................................................................................................... 227 ...
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Rev.4.00 Nov. 02, 2005 Page xvi of xxiv ...
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Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 2 Figure 1.2 Pin Arrangement (FP-64E)............................................................................................ 3 Figure 1.3 Pin Arrangement (FP-48F, FP-48B).............................................................................. 4 Section 2 CPU Figure 2.1 Memory Map................................................................................................................. 8 Figure 2.2 CPU Registers ............................................................................................................... 9 Figure 2.3 Usage ...
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Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 65 Figure 5.2 Block Diagram of System Clock Generator ................................................................ 65 Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 66 Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 66 ...
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Figure 11.2 Free-Running Counter Operation ............................................................................ 142 Figure 11.3 Periodic Counter Operation..................................................................................... 143 Figure 11.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 143 Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 144 ...
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Figure 13.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 180 Figure 13.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 181 Figure 13.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 183 Figure ...
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Appendix B I/O Port Block Diagrams Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 276 Figure B.2 Port 1 Block Diagram (P14) ..................................................................................... 277 Figure B.3 Port 1 Block Diagram (P16, P15, P12, P10)............................................................. 278 Figure B.4 Port 1 Block ...
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Rev.4.00 Nov. 02, 2005 Page xxii of xxiv ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 16 Table 2.2 Data Transfer Instructions....................................................................................... 17 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 18 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 19 ...
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Table 7.5 Additional-Program Data Computation Table ........................................................ 89 Table 7.6 Programming Time ................................................................................................. 89 Section 10 Timer V Table 10.1 Pin Configuration.................................................................................................. 117 Table 10.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 119 Section 11 Timer W ...
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Features High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions Various peripheral functions Timer V (8-bit timer) Timer W (16-bit timer) Watchdog timer ...
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Section 1 Overview 1.2 Internal Block Diagram generator P17/IRQ3/TRGV P16 P15 P14/IRQ0 P12 P11 P10 P22/TXD P21/RXD P20/SCK3 P57 P56 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Note: * Can also be used for the emulator. Rev.4.00 Nov. ...
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Pin Arrangement P14/IRQ0 52 P15 53 P16 P17/IRQ3/TRGV ...
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Section 1 Overview P14/IRQ0 37 P15 38 P16 39 P17/IRQ3/TRGV PB3/AN3 45 PB2/AN2 46 PB1/AN1 47 PB0/AN0 48 Notes: Do not connect NC pins (these pins are not connected to the ...
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Pin Functions Table 1.1 Pin Functions Type Symbol FP-64E Power source pins Clock pins OSC1 11 OSC2 10 RES System 7 control TEST 8 NMI Interrupt 35 ...
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Section 1 Overview Type Symbol FP-64E Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer W FTCI 36 FTIOA FTIOD Serial com- TXD 46 munication interface RXD 45 (SCI) SCK3 44 A/D AN3 to ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight ...
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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figure 2.1 shows the memory map. (Flash memory version) H'0000 H'0033 H'0034 H'3FFF ...
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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register ...
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), ...
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Section 2 CPU Bit Bit Name Initial Value undefined 5 H undefined 4 U undefined 3 N undefined 2 Z undefined 1 V undefined 0 C undefined Rev.4.00 Nov. 02, 2005 Page 12 of 304 ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn : General register General register General register R RnH : ...
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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...
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Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) MOVTPE B Rs POP W/L ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register (immediate byte ...
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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – ...
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a ...
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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B ...
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Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand ...
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Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set ...
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Section 2 CPU Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two ...
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Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...
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Section 2 CPU Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A ...
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Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, ...
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Section 2 CPU Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ...
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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Effective Address Calculation PC contents ...
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock ( ) or a subclock ( edge the next rising edge is called one state. A bus cycle consists of two states ...
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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, ...
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Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...
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Section 2 CPU Bit manipulation for two registers assigned to the same address Example: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the series of this LSI.) Figure 2.13 ...
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Prior to executing BSET instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BSET instruction executed instruction BSET #0, @PDR5 After executing BSET instruction P57 P56 Input/output Input Input Pin state ...
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Section 2 CPU Prior to executing BSET instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 BSET instruction executed ...
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Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. ...
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Section 2 CPU Prior to executing BCLR instruction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 BCLR instruction executed ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. ...
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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table ...
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Register Descriptions Interrupts are controlled by the following registers. Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge ...
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value ...
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Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, and external pin interrupts. Bit Bit Name Initial Value 7 IENDT IENWP IEN3 IEN0 0 ...
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Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Bit Bit Name Initial Value 7 IRRDT ...
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Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value IWPF5 0 4 IWPF4 0 3 IWPF3 0 2 IWPF2 0 1 ...
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Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by ...
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WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending ...
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Section 3 Exception Handling When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit is set to 1 ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC Lower 8 bits ...
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Section 3 Exception Handling Rev.4.00 Nov. 02, 2005 Page 52 of 304 REJ09B0143-0400 Figure 3.3 Interrupt Sequence ...
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Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, ...
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Section 3 Exception Handling Rev.4.00 Nov. 02, 2005 Page 54 of 304 REJ09B0143-0400 ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
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Section 4 Address Break 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value 7 RTINTE 1 6 CSEL1 0 5 CSEL0 0 4 ACMP2 0 3 ACMP1 0 2 ACMP0 0 1 DCMP1 ...
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When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When ...
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Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the ...
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Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set the combination of the address ...
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch Address 025C bus Interrupt request Figure 4.2 Address Break Interrupt ...
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Usage Notes When an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch instruction is not satisfied is executed (see figure 4.3), note that an address ...
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Section 4 Address Break [Register setting] ABRKCR=H'80 BAR=H'0144 External interrupt MOV instruction instruction prefetch prefetch Address bus 0142 Address break interrupt request ABIF External interrupt acceptance Figure 4.4 Operation when Another Interrupt is Accepted at Address Break Setting When an ...
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ADBRKCR = H'80 BAR = H'0150 Address bus Address break interrupt request Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to [Program] 0134 BNE 0136 NOP 0138 NOP . 0150 MOV.B ...
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Section 4 Address Break Rev.4.00 Nov. 02, 2005 Page 64 of 304 REJ09B0143-0400 ...
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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. ...
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Section 5 Clock Pulse Generators 5.1.1 Connecting Crystal Resonator Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A resonator ...
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External Clock Input Method Connect an external clock signal to pin OSC connection. The duty cycle of the external clock signal must 55%. Figure 5.6 Example of External Clock Input 5.2 Prescalers 5.2.1 Prescaler S Prescaler ...
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Section 5 Clock Pulse Generators 5.3.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC 1 oscillator circuit to prevent induction from interfering with ...
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Section 6 Power-Down Modes This LSI has five modes of operation after a reset. These include a normal active mode and three power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
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Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls ...
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Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 states 1 0 128 states 1 ...
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value 7 SMSEL DTON 0 4 MA2 0 3 MA1 0 2 MA0 ...
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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value MSTS3 0 4 MSTAD 0 3 MSTWD 0 2 ...
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing ...
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Legend: X: Don’t care. When a state transition is performed while SMSEL is 1, timer V, ...
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Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an ...
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Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The ...
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Section 6 Power-Down Modes Rev.4.00 Nov. 02, 2005 Page 78 of 304 REJ09B0143-0400 ...
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The features of the 20-kbyte (4 kbytes of them are the control program area) flash memory built into HD64F3672 are summarized below. Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed ...
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Section 7 ROM H'0000 Erase unit H'0080 1kbyte H'0380 H'0400 Erase unit H'0480 1kbyte H'0780 H'0800 Erase unit H'0880 1kbyte H'0B80 H'0C00 Erase unit H'0C80 1kbyte H'0F80 H'1000 Erase unit H'1080 16 kbytes H'4F80 Figure 7.1 Flash Memory Block Configuration ...
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Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit ...
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Section 7 ROM 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value 7 FLER ...
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Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, and EBR1. Bit Bit Name Initial Value 7 FLSHE — All ...
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Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the ...
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Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 MHz 9,600 bps MHz 4,800 bps 4 ...
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Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: ...
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Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in ...
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Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table 7.6 Programming Time ...
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Section 7 ROM 5. For a dummy write to a verify address, write 1-byte data H' address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write ...
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Increment address No No Note: * The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Erase start SWE bit 1 Wait 1 ...
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Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled ...
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This LSI has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Note: The address area H'F780 ...
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Section 8 RAM Rev.4.00 Nov. 02, 2005 Page 94 of 304 REJ09B0143-0400 ...
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The group of this LSI has twenty-six general I/O ports and four general input-only ports. Port large current port, which can drive 20 mA (@V Any of these ports can become an input port immediately after a ...
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W 7 IRQ3 IRQ0 ...
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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 ...
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 ...
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P15 pin Register PCR1 Bit Name PCR15 Setting value 0 1 P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Setting value Legend: X: Don't care. P12 pin Register PCR1 Bit Name PCR12 Setting value ...
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Section 9 I/O Ports 9.2 Port 2 Port general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have ...
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Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R P22 0 1 P21 0 0 ...
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Section 9 I/O Ports P20/SCK3 pin Register SCR3 Bit Name CKE1 Setting Value Legend: X: Don't care. 9.3 Port 5 Port general I/O port also functioning as an A/D trigger input pin and ...
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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF7 0 6 POF6 0 5 WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 ...
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Section 9 I/O Ports 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W 7 PCR57 0 6 PCR56 0 ...
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Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value PUCR55 0 4 PUCR54 0 3 PUCR53 ...
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Section 9 I/O Ports P55/WKP5/ADTRG pin Register PMR5 Bit Name WKP5 Setting Value 0 1 Legend: X: Don't care. P54/WKP4 pin Register PMR5 Bit Name WKP4 Setting Value 0 1 Legend: X: Don't care. P53/WKP3 pin Register PMR5 Bit Name ...
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P51/WKP1 pin Register PMR5 Bit Name WKP1 Setting Value 0 1 Legend: X: Don't care. P50/WKP0 pin Register PMR5 Bit Name WKP0 Setting Value 0 1 Legend: X: Don't care. 9.4 Port 7 Port general I/O port ...
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Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R PCR76 0 5 PCR75 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV Bit Name OS3 to OS0 Setting Value 0000 Other than the above values Legend: X: Don't care. P75/TMCIV pin Register ...
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Section 9 I/O Ports 9.5 Port 8 Port general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W ...
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Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R P84 0 3 P83 0 2 P82 0 1 P81 ...
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Section 9 I/O Ports P83/FTIOC pin Register TIOR1 Bit Name IOC2 IOC1 Setting Value Legend: X: Don't care. P82/FTIOB pin Register TIOR0 Bit Name IOB2 IOB1 Setting Value ...
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P80/FTCI pin Register PCR8 Bit Name PCR80 Setting Value 0 1 9.6 Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. ...
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Section 9 I/O Ports 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R PB3 2 PB2 1 PB1 0 PB0 Rev.4.00 ...
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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...
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Section 10 Timer V TRGV Clock select TMCIV PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register ...
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Input/Output Pins Table 10.1 shows the timer V pin configuration. Table 10.1 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 10.3 Register Descriptions Time V has the following registers. Timer counter ...
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Section 10 Timer V 10.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV ...
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Bit Bit Name Initial Value R/W 2 CKS2 0 1 CKS1 0 0 CKS0 0 Table 10.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 ...
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Section 10 Timer V 10.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Bit Bit Name Initial Value R/W 7 CMFB 0 6 CMFA 0 5 OVF ...
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OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the ...
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Section 10 Timer V 10.4 Operation 10.4.1 Timer V Operation 1. According to table 10.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, ...
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Internal clock TCNTV input clock N – 1 TCNTV Figure 10.2 Increment Timing with Internal Clock TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 10.3 Increment Timing with External Clock TCNTV H'FF Overflow signal OVF ...
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Section 10 Timer V TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 10.5 CMFA and CMFB Set Timing Compare match A signal Timer V output pin Compare match A signal TCNTV Figure 10.7 Clear Timing by Compare ...
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TMRIV(External counter reset input pin ) TCNTV reset signal N – 1 TCNTV Figure 10.8 Clear Timing by TMRIV Input Section 10 Timer V N H'00 Rev.4.00 Nov. 02, 2005 Page 125 of 304 REJ09B0143-0400 ...
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Section 10 Timer V 10.5 Timer V Application Examples 10.5.1 Pulse Output with Arbitrary Duty Cycle Figure 10.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that ...
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Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 10.10. ...
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Section 10 Timer V 10.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal ...
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Address Internal write signal TCNTV TCORA Compare match signal Figure 10.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N Write to CKS1 and CKS0 Figure 10.13 Internal Clock Switching and TCNTV ...
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Section 10 Timer V Rev.4.00 Nov. 02, 2005 Page 130 of 304 REJ09B0143-0400 ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Section 11 Timer W Table 11.1 Timer W Functions Item Counter Count clock Internal clocks: , /2, /4, /8 External clock: FTCI General registers Period (output compare/input specified in capture registers) GRA Counter clearing function GRA compare match Initial output ...
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Internal clock: /2 Clock /4 selector /8 External clock: FTCI Comparator [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 ...
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Section 11 Timer W 11.2 Input/Output Pins Table 11.2 summarizes the timer W pins. Table 11.2 Pin Configuration Name Abbreviation External clock input FTCI Input capture/output FTIOA compare A Input capture/output FTIOB compare B Input capture/output FTIOC compare C Input ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W 7 CTS BUFEB 0 4 BUFEA PWMD 0 1 ...
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Section 11 Timer W 11.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value 7 CCLR 0 6 CKS2 0 5 CKS1 ...
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Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W 7 OVIE IMIED 0 2 IMIEC 0 1 IMIEB 0 0 IMIEA ...
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Section 11 Timer W Bit Bit Name Initial Value R/W 3 IMFD 0 2 IMFC 0 1 IMFB 0 0 IMFA 0 Rev.4.00 Nov. 02, 2005 Page 138 of 304 REJ09B0143-0400 Description R/W Input Capture/Compare Match Flag D [Setting conditions] ...
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Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R IOB2 0 5 IOB1 0 4 ...
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Section 11 Timer W 11.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value IOD2 0 5 ...
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Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW ...
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Section 11 Timer W 11.4 Operation The timer W has the following operating modes. Normal Operation PWM Operation 11.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When ...
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TCNT value GRA H'0000 CTS bit IMFA Figure 11.3 Periodic Counter Operation By setting a general register as an output compare register, compare match can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD ...
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Section 11 Timer W TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 11.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by ...
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TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 FTIOA GRA H'1000 FTIOB GRB Figure 11.7 Input Capture Operating Example Figure 11.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set ...
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Section 11 Timer W TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 FTIOA GRA GRC Figure 11.8 Buffer Operation Example (Input Capture) 11.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, ...
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TCNT value GRA GRB GRC GRD H'0000 FTIOB FTIOC FTIOD Figure 11.10 shows another example of operation in PWM mode. The output signals and TCNT is cleared at compare match A, and the output signals go to ...
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Section 11 Timer W Figure 11.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB ...
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TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB Figure 11.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output ...
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Section 11 Timer W TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB (TOB, TOC, and TOD = 1: initial output values ...
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Operation Timing 11.5.1 TCNT Count Timing Figure 11.14 shows the TCNT count timing when the internal clock source is selected. Figure 11.15 shows the timing when the external clock source is selected. The pulse width of the external clock ...
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Section 11 Timer W Figure 11.16 shows the output compare timing. TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 11.16 Output Compare Output Timing 11.5.3 Input Capture Timing Input capture on the rising edge, ...
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Timing of Counter Clearing by Compare Match Figure 11.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from and its cycle is N ...
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Section 11 Timer W Input capture signal TCNT GRA, GRB GRC, GRD Figure 11.20 Buffer Operation Timing (Input Capture) 11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is ...
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Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an ...
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Section 11 Timer W 11.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system ...
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Previous clock New clock Count clock N N+1 TCNT The change in signal level at clock switching is assumed rising edge, and TCNT increments the count. Figure 11.25 Internal Clock Switching and TCNT Operation Section 11 Timer ...
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Section 11 Timer W 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values ...
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Section 12 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The ...
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Section 12 Watchdog Timer 12.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The ...
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Bit Bit Name Initial Value R/W 0 WRST 0 12.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is ...
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Section 12 Watchdog Timer 12.3 Operation The watchdog timer is provided with an 8-bit counter written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. ...
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Section 13 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a ...
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Section 13 Serial Communication Interface 3 (SCI3) External SCK 3 clock Baud rate generator Clock Transmit/receive control circuit TXD RXD [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode ...
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Input/Output Pins Table 13.1 shows the SCI3 pin configuration. Table 13.1 Pin Configuration Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output 13.3 Register Descriptions The SCI3 has the following registers. Receive shift register (RSR) Receive ...
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data ...
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Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator clock source. Bit Bit Name Initial Value 7 COM 0 6 CHR ...
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Section 13 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value 1 CKS1 0 0 CKS0 0 13.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is ...
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Bit Bit Name Initial Value 3 MPIE 0 2 TEIE 0 1 CKE1 0 0 CKE0 0 Section 13 Serial Communication Interface 3 (SCI3) R/W Description R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 ...
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they ...
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Bit Bit Name Initial Value 4 FER 0 3 PER 0 2 TEND 1 1 MPBR 0 0 MPBT 0 Section 13 Serial Communication Interface 3 (SCI3) R/W Description R/W Framing Error [Setting condition] When a framing error occurs in ...
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Section 13 Serial Communication Interface 3 (SCI3) 13.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13.2 shows the relationship between the N setting in BRR ...
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Table 13.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) 2 Bit Rate Error (bits/ (%) 110 1 141 0.03 150 1 103 0.16 300 0 207 0.16 600 0 103 0.16 1200 0 51 ...
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Section 13 Serial Communication Interface 3 (SCI3) Table 13.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 6 Bit Rate Error (bit/ (%) 110 2 106 –0.44 150 2 77 0.16 300 1 155 0.16 ...