HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 11

• Manufacturer Part Number: HD64F3672FPIV
• Description: MCU 3/5V 16K I-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPIV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Section 2 CPU........................................................................................................7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling .............................................................................41
3.1
3.2
Features.................................................................................................................................. 1
Internal Block Diagram.......................................................................................................... 2
Pin Arrangement .................................................................................................................... 3
Pin Functions ......................................................................................................................... 5
Address Space and Memory Map .......................................................................................... 8
Register Configuration........................................................................................................... 9
2.2.1
2.2.2
2.2.3
Data Formats........................................................................................................................ 13
2.3.1
2.3.2
Instruction Set ...................................................................................................................... 16
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation........................................................ 27
2.5.1
2.5.2
Basic Bus Cycle ................................................................................................................... 32
2.6.1
2.6.2
CPU States ........................................................................................................................... 34
Usage Notes ......................................................................................................................... 35
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address ............................................................................... 42
Register Descriptions ........................................................................................................... 43
3.2.1
3.2.2
3.2.3
3.2.4
General Registers.................................................................................................... 10
Program Counter (PC) ............................................................................................ 11
Condition-Code Register (CCR)............................................................................. 11
General Register Data Formats ............................................................................... 13
Memory Data Formats ............................................................................................ 15
Table of Instructions Classified by Function .......................................................... 16
Basic Instruction Formats ....................................................................................... 25
Addressing Modes .................................................................................................. 27
Effective Address Calculation ................................................................................ 30
Access to On-Chip Memory (RAM, ROM)............................................................ 32
On-Chip Peripheral Modules .................................................................................. 33
Notes on Data Access to Empty Areas ................................................................... 35
EEPMOV Instruction.............................................................................................. 35
Bit Manipulation Instruction................................................................................... 35
Interrupt Edge Select Register 1 (IEGR1) .............................................................. 43
Interrupt Edge Select Register 2 (IEGR2) .............................................................. 44
Interrupt Enable Register 1 (IENR1) ...................................................................... 45
Interrupt Flag Register 1 (IRR1)............................................................................. 46
Contents
Rev.4.00 Nov. 02, 2005 Page ix of xxiv