HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 71

• Manufacturer Part Number: HD64F3672FPIV
• Description: MCU 3/5V 16K I-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPIV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.3
IENR1 enables direct transition interrupts, and external pin interrupts.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Bit Bit Name
7
6
5
4
3
2
1
0
IENDT
IENWP
IEN3
IEN0
Interrupt Enable Register 1 (IENR1)
Initial Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
Reserved
This bit is always read as 0.
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
Reserved
This bit is always read as 1.
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
Reserved
These bits are always read as 0.
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
Rev.4.00 Nov. 02, 2005 Page 45 of 304
Section 3 Exception Handling
REJ09B0143-0400