HD64F3672FPIV Renesas Electronics America, HD64F3672FPIV Datasheet - Page 84

MCU 3/5V 16K I-TEMP PB-FREE 64-L

HD64F3672FPIV

Manufacturer Part Number
HD64F3672FPIV
Description
MCU 3/5V 16K I-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3672FPIV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 4 Address Break
4.1.3
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev.4.00 Nov. 02, 2005 Page 58 of 304
REJ09B0143-0400
Break Address Registers (BARH, BARL)
Break Data Registers (BDRH, BDRL)

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