HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 208

• Manufacturer Part Number: HD6413008VX25
• Description: MCU 5V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VX25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6413008VTE25; HD6413008VTE25

7. I/O Ports
7.7.2
Table 7.11 summarizes the registers of port A.
Table 7.11 Port A Registers
Address*
H'EE009
H'FFFD9
Note:
Rev.4.00 Aug. 20, 2007 Page 162 of 638
REJ09B0395-0400
Port A
* Lower 20 bits of the address in advanced mode.
Register Descriptions
Name
Port A data direction
register
Port A data register
Port A pins
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TCLKB
PA /TP /TCLKA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 7.6 Port A Pin Configuration
2
2
1
1
0
0
21
23
20
22
PADDR
PADR
Pin functions in modes 1 and 2
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
Pin functions in modes 3 and 4
A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/A
PA (input/output)/TP (output)/TIOCA (input/output)/A
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
20
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(output)
R/W
W
R/W
Modes 1 and 2
H'00
H'00
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Initial Value
2
2
1
1
0
0
2
1
1
0
0
H'00
Modes 3 and 4
H'80
21
22
23
(output)
(output)
(output)