HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 441

MCU 5V 0K 100-TQFP

HD6413008VX25

Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD6413008VX25

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
2. Inverse Convention (SDIR = SINV = O/E = 1)
With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3008, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For
parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both
transmission and reception.
(Z)
(Z)
Ds
Ds
A
A
D0
D7
Z
Z
D1
D6
Z
Z
D2
D5
A
A
D3
D4
A
Z
D4
D3
A
Z
D5
D2
Z
A
Rev.4.00 Aug. 20, 2007 Page 395 of 638
D6
D1
A
A
D7
D0
A
A
13. Smart Card Interface
Dp
Dp
Z
Z
(Z)
(Z)
REJ09B0395-0400
State
State

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