HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 368

• Manufacturer Part Number: HD6413008VX25
• Description: MCU 5V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VX25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6413008VTE25; HD6413008VTE25

12. Serial Communication Interface
• Full-duplex communication
• The following settings can be made for the serial data to be transferred:
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
• Four types of interrupts
Features of the smart card interface are listed below.
• Asynchronous communication
• Built-in baud rate generator with selectable bit rates
• Three types of interrupts
Rev.4.00 Aug. 20, 2007 Page 322 of 638
REJ09B0395-0400
⎯ Data length:
⎯ Receive error detection:
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
⎯
⎯
clock from the SCK pin
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently.
⎯ Data length: 8 bits
⎯ Parity bits generated and checked
⎯ Error signal output in receive mode (parity error)
⎯ Error signal detect and automatic data retransmit in transmit mode
⎯ Supports both direct convention and inverse convention
Transmit-data-empty, receive-data-full, and transmit/receive-error interrupts are requested
independently.
LSB-first or MSB-first transfer
Inversion of data logic level
8 bits
overrun errors