HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 32

• Manufacturer Part Number: HD6413008VX25
• Description: MCU 5V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VX25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6413008VTE25; HD6413008VTE25

Figure 5.3
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Figure 5.7
Figure 5.8
Section 6 Bus Controller
Figure 6.1
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Figure 6.13
Figure 6.14
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Figure 6.16
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Figure 6.23
Figure 6.24
Rev.4.00 Aug. 20, 2007 Page xxx of xliv
REJ09B0395-0400
Access Sizes and Data Alignment Control (8-Bit Access Area) ........................ 122
Access Sizes and Data Alignment Control (16-Bit Access Area) ...................... 123
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address) .......................................................................... 127
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address) ........................................................................... 128
Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)
(Word Access).................................................................................................... 129
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
(Word Access).................................................................................................... 132
Example of Wait State Insertion Timing............................................................ 133
Timing of Setting of IRQnF ............................................................................... 88
Process Up to Interrupt Acceptance when UE = 1 ............................................. 93
Interrupt Masking State Transitions (Example) ................................................. 95
Process Up to Interrupt Acceptance when UE = 0 ............................................. 96
Interrupt Exception Handling Sequence............................................................. 97
Contention between Interrupt and Interrupt-Disabling Instruction .................... 99
Block Diagram of Bus Controller....................................................................... 102
Access Area Map for Each Operating Mode...................................................... 116
Memory Map in 16-Mbyte Mode....................................................................... 117
CSn Signal Output Timing (n = 0 to 7) .............................................................. 120
Sample Address Output in Each Address Update Mode
(Basic Bus Interface, 3-State Space) .................................................................. 120
Example of Consecutive External Space Accesses in Address Update
Mode 2 ............................................................................................................... 121
Bus Control Signal Timing for 8-Bit, Three-State-Access Area ........................ 125
Bus Control Signal Timing for 8-Bit, Two-State-Access Area .......................... 126
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address) .......................................................................... 130
Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)
(Byte Access to Odd Address) ........................................................................... 131
Example of Idle Cycle Operation (ICIS1 = 1).................................................... 134
Example of Idle Cycle Operation (ICIS0 = 1).................................................... 135
Example of Idle Cycle Operation ....................................................................... 136
Example of External Bus Master Operation....................................................... 138
ASTCR Write Timing ........................................................................................ 139
DDR Write Timing............................................................................................. 139
BRCR Write Timing .......................................................................................... 140