DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 186
![MCU 3/5V 32K J-TEMP PB-FREE 64-Q](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 11 Timer V
11.3.2
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
11.3.3
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Rev. 4.00 Mar. 15, 2006 Page 152 of 556
REJ09B0026-0400
Bit
7
6
5
4
3
Bit Name
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
Time Constant Registers A and B (TCORA, TCORB)
Timer Control Register V0 (TCRV0)
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
Counter Clear 1 and 0
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.
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