DF36034HJV Renesas Electronics America, DF36034HJV Datasheet - Page 348
DF36034HJV
Manufacturer Part Number
DF36034HJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034HJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 15 Controller Area Network for Tiny (TinyCAN)
Note:
Rev. 4.00 Mar. 15, 2006 Page 314 of 556
REJ09B0026-0400
Bit
7 to 5
4
3, 2
1
0
TCIRR1
*
Bit Name
—
WUPI
—
OVRI
EMPI
Only 1 can be written to clear the flag.
Initial
Value
All 0
0
All 0
0
0
R/W
—
R/(W)* Wakeup Interrupt Flag
—
R
R
Description
Reserved
These bits are always read as 0.
Status flag indicating detection of a dominant bit on the
CAN bus while the LSI is in standby mode. This flag can
be set to 1 only in standby mode.
[Setting condition]
When the falling edge of HRXD is detected in standby
mode
[Clearing condition]
When 1 is written to this bit
Reserved
These bits are always read as 0.
Unread Message Interrupt Flag
Status flag indicating that a new message has been
received regardless of existence of an unread message.
The NMC bit in MCn0 (n = 0 to 3) will determine how to
handle the newly received message: NMC = 1 selects
overwrite and NMC = 0 selects overrun (ignore).
[Setting condition]
When a new message is received with the MBIMR
corresponding to the receive message cleared to 0 and
the corresponding bit in RXPR or RFPR set to 1
[Clearing condition]
When all bits in UMSR are cleared to 0
Mailbox Empty Interrupt Flag
Status flag indicating that the next transmit message can
be written to the Mailbox.
[Setting condition]
When TXPR is cleared to 0 by completion of transmission
or completion of transmission cancellation
[Clearing condition]
When TXACK and ABACK is cleared to 0
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