DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 249
![MCU 3/5V 56K PB-FREE J-TEMP 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36037FZJV
Manufacturer Part Number
DF36037FZJV
Description
MCU 3/5V 56K PB-FREE J-TEMP 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36037FZJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 12.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty
in complementary PWM mode (for one phase).
Set GRB_0 to H'0000 or a value equal to or more than GRA_0, and the waveform with a duty
cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles
can easily be changed, including the above settings, during operation. For details on buffer
operation, see section 12.4.8, Buffer Operation.
Other than TPSC2 = TPSC1 = TPSC0 = 0
Set GRB_0 to satisfy the following expression: GRA_0 + 1 < GRB_0 < H'FFFF, and the
waveform with a duty cycle of 0% and 100% can be output. For details on 0%- and 100%-duty
cycle waveform output, see Setting GR Value in Complementary PWM Mode: C, Outputting a
waveform with a duty cycle of 0% and 100% in section 12.4.7, Complementary PWM Mode.
TPSC2 = TPSC1 = TPSC0 = 0
Rev. 4.00 Mar. 15, 2006 Page 215 of 556
Section 12 Timer Z
REJ09B0026-0400
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