DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 432
![MCU 3/5V 56K PB-FREE J-TEMP 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36037FZJV
Manufacturer Part Number
DF36037FZJV
Description
MCU 3/5V 56K PB-FREE J-TEMP 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36037FZJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 18 A/D Converter
18.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As indicated in figure 18.2, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
Rev. 4.00 Mar. 15, 2006 Page 398 of 556
REJ09B0026-0400
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total conversion
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1):
(2):
t
t
t
D
SPL
CONV
:
:
:
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
A/D conversion time
Figure 18.2 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) has passed after the ADST bit is set to 1, then
t
CONV
D
and the input sampling time. The
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