DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 404
![MCU 3/5V 56K PB-FREE J-TEMP 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36037FZJV
Manufacturer Part Number
DF36037FZJV
Description
MCU 3/5V 56K PB-FREE J-TEMP 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36037FZJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 404 of 594
- Download datasheet (4Mb)
Section 16 Synchronous Serial Communication Unit (SSU)
16.4.6
Operation in Four-Line Bus Communication Mode
Four-line bus communication mode is a mode which communicates with the four-line bus; a clock
line, a data input line, a data output line, and a chip select line. This mode includes bidirectional
mode in which the data input line and the data output line function as a single pin. The data input
line and the data output line are changed according to the settings of the MSS and BIDE bits in
SSCRH. For details, refer to section 16.4.3, Relationship between Data Input/Output Pin and Shift
Register. In this mode, relationship between clock polarity and phase, and data can be set by the
CPOS and CPHS bits in SSMR. For details, refer to section 16.4.2, Relationship between Clock
Polarity and Phase, and Data.
When the SSU is set as a master device, the chip select line controls output. When the SSU is set
as a slave device, the chip select line controls input. When the SSU is set as a master device, the
chip select line controls output of the SCS pin or controls output of a general port by setting the
CSS1 bit in SSCRH to 1. When the SSU is set as a slave device, the chip select line sets the SCS
pin as an input pin by setting the CSS1 and CSS0 bits in SSCRH to 01.
In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed
in MSB-first order.
Rev. 4.00 Mar. 15, 2006 Page 370 of 556
REJ09B0026-0400
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