DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 27

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode
Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 273
Figure 14.7 Example of SCI3 Reception in Asynchronous Mode
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 276
Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 277
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 278
Figure 14.10 Example of SCI3 Transmission in Clocked Synchronous Mode........................... 279
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 280
Figure 14.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 281
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 282
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Figure 14.15 Example of Inter-Processor Communication Using Multiprocessor Format
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 287
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 288
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 289
Figure 14.18 Example of SCI3 Reception Using Multiprocessor Format
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 293
Section 15 Controller Area Network for Tiny (TinyCAN)
Figure 15.1 TinyCAN Block Diagram........................................................................................ 296
Figure 15.2 Standard Format and Extended Format ................................................................... 319
Figure 15.3 Message Data Configuration ................................................................................... 323
Figure 15.4 Reset Clearing Flowchart ........................................................................................ 324
Figure 15.5 CAN Bit Configuration ........................................................................................... 325
Figure 15.6 Transmission Request Flowchart............................................................................. 327
Figure 15.7 Internal Arbitration at Transmission Caused by TXCR/TXPR Setting................... 329
Figure 15.8 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
Figure 15.9 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
Figure 15.10 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
Figure 15.11 Internal Arbitration at Error Detection (MBn in TXCR = 0 and DART = 0)........ 333
Figure 15.12 Internal Arbitration at Error Detection (MBn in TXCR = 1)................................. 334
Figure 15.13 Internal Arbitration at Error Detection (DART = 1).............................................. 335
Figure 15.14 Message Reception Flowchart............................................................................... 336
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 272
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 274
(MBn in TXCR = 0 and DART = 0)........................................................................ 330
(MBn in TXCR = 1) ................................................................................................ 331
(DART = 1) ........................................................................................................... 332
(Clocked Synchronous Mode)............................................................................... 284
(Transmission of Data H'AA to Receiving Station A) .......................................... 286
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 290
Rev. 4.00 Mar. 15, 2006 Page xxv of xxxii