DF36037FZJV Renesas Electronics America, DF36037FZJV Datasheet - Page 393

• Manufacturer Part Number: DF36037FZJV
• Description: MCU 3/5V 56K PB-FREE J-TEMP 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36037FZJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4
16.4.1
Transfer clock can be selected from seven internal clocks and an external clock. When this module
is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSCRH to 1.
When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output
state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to
CKS0 bits in SSMR. When the MSS bit is 0, an external clock is selected and the SSCK pin is in
the input state.
16.4.2
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSCRL and the CPOS and CPHS bits in SSMR. Figure 16.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is
started from MSB to LSB.
Operation
Transfer Clock
Relationship between Clock Polarity and Phase, and Data
Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 359 of 556
REJ09B0026-0400