HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 191

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.5.3
When DRAM space is accessed, the row address and column address are multiplexed. The address
multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number
of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of
MXC1 and MXC0 and the address multiplexing method.
Table 6.6
Note: * Row address bit A
6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space,
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
Row
address
Column
address
Address Multiplexing
DRCRB
MXC1 MXC0 Bits
0
1
—
Data Bus
Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
0
1
0
1
—
Column
Address
8 bits
9 bits
10 bits
Illegal
setting
—
20
is not multiplexed in 1-Mbyte mode.
16-bit organization DRAM can be connected directly.
Address
A
A
A
A
—
A
23
23
23
23
23
to A
to A
to A
to A
to A
13
13
13
13
13
Pins
A
A
A
A
— — — — — — — — — — — — —
A
12
20
12
12
12
* A
A
A
A
A
11
19
20
11
11
* A
A
A
A
A
10
15
20
18
19
10
* A
to D
15
A
A
A
A
Rev. 4.00 Jan 26, 2006 page 167 of 938
to D
9
17
18
19
9
8
, is enabled, while in 16-bit DRAM
A
A
A
A
A
0
8
16
17
18
8
, are enabled.
A
A
A
A
A
7
15
16
17
7
A
A
A
A
A
6
14
15
16
6
Section 6 Bus Controller
A
A
A
A
A
5
13
14
15
5
A
A
A
A
A
REJ09B0276-0400
4
12
13
14
4
A
A
A
A
A
3
11
12
13
3
A
A
A
A
A
2
10
11
12
2
A
A
A
A
A
1
9
10
11
1
A
A
A
A
A
0
8
9
10
0