HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 791

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8. Block transfer instructions
Notes: 1. The number of states is the number of states required for execution when the
Mnemonic
EEPMOV. B
EEPMOV. W
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
instruction and its operands are located in on-chip memory. For other cases see section
A.3.
synchronization with the E clock is variable.
—
—
Instruction Length (bytes)
Addressing Mode and
4
4
Operation
if R4L
else next;
if R4
else next;
repeat @R5
until
repeat @R5
until
0
0
R5+1
R6+1
R4L 1
R4L=0
R5+1
R6+1
R4 1
R4=0
Rev. 4.00 Jan 26, 2006 page 767 of 938
@R6
@R6
R4
R5
R6
R5
R6
R4L
I
Condition Code
Appendix A Instruction Set
H N Z
REJ09B0276-0400
V C
4n*
4n*
States*
8+
8+
No. of
2
2
1