HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 370

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 16-Bit Timer
Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables
the interrupt requested by the IMFB1 flag when IMFB1 is set to 1.
Bit 5
IMIEB1
0
1
Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables
the interrupt requested by the IMFB0 flag when IMFB0 is set to 1.
Bit 4
IMIEB0
0
1
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag B2 (IMFB2): This status flag indicates GRB2
compare match or input capture events.
Bit 2
IMFB2
0
1
Rev. 4.00 Jan 26, 2006 page 346 of 938
REJ09B0276-0400
IMIB1 interrupt requested by IMFB1 flag is disabled
IMIB1 interrupt requested by IMFB1 flag is enabled
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 flag is enabled
Description
Description
Description
[Clearing condition]
Read IMFB2 when IMFB2 =1, then write 0 in IMFB2.
[Setting conditions]
TCNT2 = GRB2 when GRB2 functions as an output compare register.
TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as
an input capture register.
(Initial value)
(Initial value)
(Initial value)