HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 194

IC H8 MCU FLASH 128K 100-QFP

HD64F3067RF20

Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3067RF20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 6 Bus Controller
6.5.7
In the H8/3067 Group, provision is made for the DRAM RAS precharge time by always inserting
one RAS precharge state (T
by setting the TPC bit to 1 in DRCRB. The optimum number of T
to the DRAM connected and the operating frequency of the H8/3067 Group chip. Figure 6.19
shows the timing when two T
When the TCP bit is set to 1, two T
Rev. 4.00 Jan 26, 2006 page 170 of 938
REJ09B0276-0400
Read access
Write access
Note: n = 2 to 5
Precharge State Control
Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)
(UCAS /LCAS)
(UCAS /LCAS)
PB
PB
CSn (RAS)
4
4
D
RD(WE)
RD(WE)
D
A
/PB
/PB
15
23
15 to
to D
5
to A
5
AS
D
p
0
0
0
) when DRAM space is accessed. This can be changed to two T
p
states are inserted.
p
states are also used for CAS-before-RAS refresh cycles.
T
p1
T
p2
High level
High level
Row
Tr
p
cycles should be set according
Column
T
c1
T
c2
p
states

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